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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT175 Quad D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jul 08
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
FEATURES * Four edge-triggered D flip-flops * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT175
The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All Qn outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL PARAMETER propagation delay CP to Qn, Qn MR to Qn tPLH propagation delay CP to Qn, Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 17 15 83 3.5 32 16 16 54 3.5 34 ns ns MHz pF pF CONDITIONS HC CL = 15 pF; VCC = 5 V 17 15 16 19 ns ns HCT UNIT
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
ORDERING INFORMATION TYPE NUMBER 74HC175N; 74HCT175N 74HC175D; 74HCT175D 74HC175DB; 74HCT175DB 74HC175PW; 74HCT175PW PACKAGE NAME DIP16 SO16 SSOP16 TSSOP16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm
74HC/HCT175
VERSION SOT38-1 SOT109-1 SOT338-1 SOT403-1
plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PIN DESCRIPTION PIN NO. 1 2, 7, 10, 15 3, 6, 11, 14 4, 5, 12, 13 8 9 16 SYMBOL MR Q0 to Q3 Q0 to Q3 D0 to D3 GND CP VCC NAME AND FUNCTION master reset input (active LOW) flip-flop outputs complementary flip-flop outputs data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODES MR reset (clear) load "1" load "0" Note 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH CP transition X = don't care L H H CP X Dn X h I Qn L H L Qn H L H OUTPUTS
Fig.5 Logic diagram.
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CP to Qn, Qn propagation delay MR to Qn, Qn output transition time +25 typ. 55 20 16 tPHL/ tPLH 50 18 14 tTHL/ tTLH 19 7 6 tW clock pulse width HIGH or LOW 80 16 14 tW master reset pulse width 80 LOW 16 14 trem removal time MR to CP 5 5 5 tsu set-up time Dn to CP hold time CP to Dn maximum clock pulse frequency 80 16 14 th 25 5 4 fmax 6.0 30 35 22 8 6 19 7 6 -33 -12 -10 3 1 1 2 0 0 25 75 89 -40 to +85 max. min. 175 35 30 150 30 26 75 15 13 100 20 17 100 20 17 5 5 5 100 20 17 30 6 5 4.8 24 28 max. 220 44 37 190 38 33 95 19 16 120 24 20 120 24 20 5 5 5 120 24 20 40 8 7 4.0 20 24 ns ns ns ns -40 to +125 min. max. 265 53 45 225 45 38 110 22 19 ns ns ns ns
74HC/HCT175
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 MHz 2.0 4.5 6.0 Fig.6 Fig.7 Fig.7 Fig.8 Fig.8 Fig.6 Fig.6 Fig.8 WAVEFORMS
Fig.6
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT175
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT MR CP Dn
UNIT LOAD COEFFICIENT 1.00 0.60 0.40
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL tPLH tTHL/ tTLH tW tW trem tsu th fmax propagation delay CP to Qn, Qn propagation delay MR to Qn propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time Dn to CP hold time CP to Dn maximum clock pulse frequency 20 20 5 16 5 25 +25 typ. 19 22 19 7 12 11 -10 5 0 49 -40 to +85 max. min. 33 38 35 15 25 25 5 20 5 20 max. 41 48 44 19 30 30 5 24 5 17 -40 to +125 min. max. 50 57 53 22 ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.8 Fig.8 Fig.6 Fig.6 Fig.8 Fig.8 Fig.7 Fig.7 Fig.6 UNIT VCC (V) WAVEFORMS TEST CONDITIONS
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
AC WAVEFORMS
74HC/HCT175
(1)
HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the clock (CP) to outputs (Qn, Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency.
Fig.7
Waveforms showing the data set-up and hold times for the data input (Dn).
(1)
HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Qn, Qn) propagation delays and the master reset to clock (CP) removal time.
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
74HC/HCT175
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1998 Jul 08
8
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1998 Jul 08
9
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150AC EIAJ EUROPEAN PROJECTION A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o
ISSUE DATE 94-01-14 95-02-04
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
74HC/HCT175
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
74HC/HCT175
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: * Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
1998 Jul 08
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Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger
REPAIRING SOLDERED JOINTS
74HC/HCT175
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1998 Jul 08
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